1. Field of the Invention
This application relates generally to a semiconductor device and a method of producing such.
2. Description of the Related Art
Semiconductor devices, particularly integrated circuits using MOS transistors, are increasingly being highly integrated. MOS transistors in integrated circuits have been downsized to nano sizes as the integration level is increased. As MOS transistors are downsized, problems arise such as difficulty in leaking current control. For that reason, further downsizing is difficult. In order to resolve these problems, a surrounding gate transistor (SGT) structure has been proposed in which the source, gate and drain are provided on a substrate in the vertical direction and the gate surrounds an island-shaped semiconductor layer.
In order to reduce power consumption in SGTs, it is preferable for resistance to be reduced in the source, gate and drain. In particular, in reducing the resistance of the gate electrode, it is desirable to use metal in the gate electrode. However, contamination of manufacturing equipment by metal and contamination of semiconductor devices produced by that manufacturing equipment is not desirable. Accordingly, processes subsequent to the forming of the metal gate electrode need to be special processes such as those that constantly control such metal contamination.
Patent Literature 1 discloses a method for producing an SGT satisfying to a certain extent the various conditions stated above.    [Patent Literature 1] International Laid-Open Patent Publication 2009/110049
However, in Patent Literature 1 the protection of semiconductor manufacturing equipment and semiconductor devices from metal contamination is imperfect. For example, in Patent Literature 1 the gate electrode is formed by planarizing the gate metal using CMP (Chemical Mechanical Polishing) and then etching this material. At this time, the gate metal is not covered by other materials and is exposed. In addition, the gate metal is similarly exposed during the process of wet etching the nitride film hard mask and nitride film sidewall. Consequently, there is a concern that the CMP device, the gate etching device and the nitride film wet etching device could be contaminated by metal in the course of producing the SGT. Hence, there is a possibility that a semiconductor device produced through such a metal device could be contaminated by metal.
In addition, when forming a metal-semiconductor compound through etching in Patent Literature 1, the gate metal is exposed. Consequently, per Patent Literature 1, the gate metal needs to be tantalum or some other material that is not etched by the chemicals used when forming the metal-semiconductor compound.
In addition, another problem is that similar to MOS transistors, as SGTs are downsized parasitic capacitance occurs in the multi-layered wiring and through this the operating speed of the SGT declines.
In consideration of the foregoing, it is an objective of the present invention to provide a semiconductor device having a structure that controls metal contamination of semiconductor manufacturing equipment and semiconductor devices in semiconductor manufacturing processes while having good characteristics, and a method of producing such a device.